Industrial power supplies need to fulfill special requirements, such as low losses (to reduce efforts on cabinet cooling), high power density (to reduce space requirements), but also high reliability and ruggedness, along with features not commonly found in standard power supplies such as easy paralleling, remote control, and certain overload and protection features. At the same time, the EMI and stability requirements are more stringent than in other applications.

This picture shows the inside of a cabinet, with power supplies and control circuits mounted on standardized rails, as well as the high- and low power wiring to connect to the machines to be controlled. Siemens AG 2008, Alle Rechte vorbehalten Click on image to enlarge.

And, with the new EuP guidelines coming up, additional requirements are coming up that impact the design of these power supplies. The main improvements must include reduced component count, weight, and size, as well as efficiency across the whole output power range and low standby consumption.

In this article, a design example of a 400W power supply is being analyzed in detail, showing the use of power supply modules for both the primary and secondary side, as well as other ways of improving the performance. Beyond all improvements on the electrical side, the identical form factor of the modules allows for a very elegant and compact mechanical design, as well as a reduction of mounting and logistics cost. The fact that both modules are available in different power ratings does significantly shorten the time-to-market, should a different output power requirement come up.

This diagram shows the different stages of a industrial power supply, indicating the main characteristics each stage impacts. Click on image to enlarge.

The PFC stage ("Power Factor Correction"), together with the bus or DC link capacitor, is key to many different factors that cannot be optimized independently. Most power supplies now use an active PFC circuit, that means, a boost converter that ensures that the input current is in phase with the input voltage, minimizing the sine wave distortions at the input. This reduces the conducted EMI and enables a wide-range input (85VAC - 265VAC), and the boost converter will adjust its duty cycle to pull input current according to the input voltage, and regulate the voltage at the bus capacitor, typically to 350V - 400V. But, if the boost converter is not active (e.g., at startup), current can flow through the input rectifier and the boost inductor and diode into the then empty bus capacitor, causing a high in-rush current. Additional circuits are needed to implement a current limiter to avoid this problem, that otherwise may trigger the grid fuses. With more stringent requirements to holdup time and brownout protection, as in high-reliability or mission-critical applications, the bus capacitor needs to be increased, further driving the inrush current up. In some cases, a NTC resistor is used, but in the case of a "warm" start (e.g. blackout), the NTC is still hot and does not offer protection. According to DIN-EN 61204, the test method has two scenarios, with 70% of the rated input voltage for 20ms, and 40% of the input voltage for 100ms " especially the second is a pretty severe situation for power supplies without active PFC.

The PWM stage ("Pulse width modulation") is the main converter stage. Here, the DC voltage is chopped into square waves of a higher frequency, consequently a much smaller transformer can be used to convert to another voltage level and provide isolation. Not all topologies actually use square waves with varying duty cycle, some use changing frequencies whereas others work by varying the phase between two pulse trains. This stage mainly determines converter efficiency and load regulation. The converter efficiency is important for many reasons: First, the cost of operating the power supply. Second, the heat it generates needs to be cooled away by cabinet cooling. Third, larger thermal components are more expensive and space consuming. All three factors contribute to the life cycle cost of the power supply.

The choice of converter topology is critical for efficiency, but also for radiated (and conducted) EMI, since the harder the power switches are switching, higher dI/dt and dV/dt in conjunction with high current and voltage levels are being produced, and this leads to significant production of harmonics of the switching frequency. Resonant or quasi-resonant topologies excel, but are harder to design and, in particular resonant topologies, are difficult to implement across a wide load range. As described later in this article, the LLC topology solves this problem very elegantly, with limited switching frequency variation across a wide load range, and soft switching.

The PWM stage is also at the center of all protection functions needed. In the case of current-mode converters, a cycle-by-cycle current limiter will protect the power supply against most output problems, usually in combination with a thermal shutdown.

The SR stage ("Synchronous rectification") converts the AC voltage from the transformer back to DC. Since the voltages are low, currents tend to be high so conduction loss in the rectifiers must be minimized. Where silicon PN junction diodes have a forward voltage of 0.7V, the same parameter for Schottky diodes is 0.4V, and for even lower voltage drop, MOSFETs are used. Here, the voltage drop is determined by the R_DS(ON) and the output current, and can be much lower. But, with MOSFETs being active devices, they need a proper gate drive signal to perform, as this circuit demonstrates. If well designed, the power dissipation in this stage can be strongly reduced, further improving the efficiency. And, with modern low-inductance packages, the design can be very compact and robust.

Continuous Conduction Mode ("CCM") Power Factor Correction

The schematic of the PFC stage Click on image to enlarge.

The input voltage coming from the input rectifier (EMI filter not shown) is fed to the PFC inductor, which, in this case, has a secondary winding to provide the supply voltage to the PFC control IC. The resistor/capacitor network before the inductor serves to reconstruct the input voltage. After the inductor, the power switch with its gate protection circuit is shown, the PFC rectifier is a StealthTM diode. A resistive divider is then used to close the feedback loop by sensing and scaling the output voltage of the PFC stage. The bus capacitor is also shown. The diode D1 is an additional protection structure.

The controller used here is the FAN4810 that includes circuits for the implementation of leading edge, average current, "boost" type power factor correction and results in a power supply that fully complies with IEC1000-3-2 specification. It also includes a TriFault Detect function to help ensure that no unsafe conditions will result from single component failure in the PFC. Gate drivers with 1A capability minimize the need for external driver circuit. Low power requirements improve efficiency and reduce component costs. The PFC also includes peak current limiting, input voltage brownout protection and an overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The clock-out signal can be used to synchronize down-stream PWM stages in order to reduce system noise.

This picture shows the behavior of a CCM PFC. Here, the thicker areas of the green curve show the current ripple, as the PFC IC draws more current at the peaks of the input voltage and no current at the zero crossings. The pink curve shows the rectified input voltage, and the blue curve the output voltage. Click on image to enlarge.

LLC Topology

One solution to increase efficiency in power supplies is to use a zero voltage switching topology [1]. In such topologies, the power switches in the circuit are turned on when there is a very low voltage across them. For a MOSFET undergoing clamped inductive switching, a simple approximation of the turn on loss, P_{ON LOSS} is given by:

where I_L is the load current flowing through the MOSFET, V_DS(SW) is the drain-to-source voltage of the MOSFET before turn on, t_ON is the turn on time and f_SW is the switching frequency.

In hard switching topologies, V_DS(SW) is the bus voltage, normally around 400V for applications having a PFC front end stage. For zero voltage switching, this voltage is reduced to the forward voltage drop of the MOSFET diode, which is something of the order of 1V. This results in a very large reduction of the turn on switching losses.

The figure below shows the block diagram of an LLC resonant converter. The core element is a resonant network which generates a phase lag between the voltage waveform on its input and current flowing into its input. The voltage waveform applied on its input is a square wave, which can easily be generated from the PFC output voltage by using a half-bridge or a full-bridge circuit.

LLC Resonant Converter Block Diagram and Zero Voltage Switching Waveforms. Click on image to enlarge.

The current flowing into the resonant network can be approximated as a sine wave, if the effects of dead time in the bridge circuit and the presence of the higher order harmonics are ignored. As the current flowing into the resonant circuit lags the fundamental of the voltage waveform, current flows in both directions through the MOSFET when it is in the ON state, as shown in the figure above. The MOSFET is turned on when current is flowing through the body diode, resulting in "zero" voltage switching. An additional benefit is lower EMI generated during turn on, as the duration of high dv/dt and di/dt transitions are much shorter, and there are usually no reverse recovery effects, which would be unavoidable in standard hard-switched applications.

As the output of the resonant circuit is periodic, it needs to be rectified. A full-wave rectifier as shown, or a rectifier with a center tap is used to achieve this.

Finally, the resonant network in an AC-DC power supply will almost always use a transformer. The transformer performs two tasks. First, it provides the necessary safety isolation needed between the primary and the secondary side. Secondly, it controls the overall voltage conversion ratio of the power supply through its turns ratio.

A certain amount of dead time is needed to remove the risk of simultaneous conduction of Q1 and Q2. Consider the turn-off waveform for Q1. The current flowing through the switch is large, close to the peak current. The voltage swing during turn off is the full bus voltage. So the turn off step is not lossless.

To ensure zero voltage switching of Q2 it is important that Q1's drain-to-source capacitance is fully charged, which means that the time for charging should not exceed the dead time. The value of the time t_SW to charge this capacitance at a given bus voltage V_BUS, current at the time of switching ISW, and an effective drain to source capacitance C_Dseff, is given by:

V_BUS is predetermined by the design constraints. If C_Dseff is zero, there is zero voltage switching of Q2, as expected. If C_Dseff is very large, there is hard switching of Q2. At light loads, where ISW is small, hard switching of Q2 will also ultimately occur at a small enough load.

Sometimes, an extra capacitor is added in parallel with each MOSFET. If it is carefully dimensioned, this has the effect of reducing the turn-off losses, without impacting the zero voltage switching performance at higher loads.

LLC resonant converters are series resonant converters with an additional inductor. So there are two inductances and one capacitance in the resonant circuit, hence the name L-L-C. The figure below shows the gain characteristics with load of an example circuit.

Example of an LLC Resonant Converter Gain Curve Click on image to enlarge.

First the voltage gain decreases with increasing frequency in the region of operation. This guarantees the phase lag required for zero voltage switching. The control circuit changes the gain of the system by changing the frequency. The difference between the minimum gain and maximum gain is quite small, so the resonant converter needs a narrow DC voltage input range. In this power supply design, the PFC stage provides the narrow input voltage range, and a continuous conduction mode PFC stage is recommended.

With a PFC stage, the input of the LLC converter is set to around 400V. If the required output voltage is 12V, and the turns ratio is 40:1, the required DC gain at nominal load is 1.2. Regardless of the load, the frequency will stay the same.

For the purposes of illustration, if the input voltage were to rise to 480V, the control circuit would need to reduce the gain to 1.0 to maintain the output voltage of 12V. In this case, the frequency would vary between 115kHz at full load and 130kHz at 20% load, as can be seen when determining at which frequencies the gain curves for different loads intersect the gain = 1.0 line. With the front end PFC stage used in the described application, some extra gain is needed for the case of a missing input half wave - the so-called "hold-up" time requirement.

Synchronous rectification

The synchronous rectification stage of the secondary side is built with the new FPP06R001 module, as shown in below schematic:

This schematic shows how the synchronous rectifier module is connected on the secondary side of the transformer Click on image to enlarge.

The diodes normally used to rectify the secondary voltage are replaced with MOSFETs. The module contains the gate drivers and the power MOSFETs in a space-saving single inline package with very wide outer leads, to reduce parasitic inductance and resistance.

This picture shows the wide leads 1 and 15 of the synchronous rectification module

Using a module instead of discrete components increases the efficiency, reduces EMI and simplifies the overall design. The specified R_DS(ON) of the MOSFETs in the module is 10% less than that of a discrete solution. The overall package inductance is 16% less, resulting in less ringing, and therefore less EMI. The small size of the gate drive loop further reduces EMI radiation and susceptibility, especially to dv/dt disturbances applied on the drain. The overall design is simpler as the layout of two difficult loops has already been done for the designer inside the module.

Parasitic impedances in the gate drive circuit Click on image to enlarge.

The above picture explains why it is so beneficial to bring the gate drivers close to the power MOSFET. The non-zero output impedance of the gate driver Z_DRV has to control the MOSFET through the parasitic impedances Z_stray1 and Z_stray2 and the gate resistance R_g, especially for turn-off. Here, a high dV/dt on the drain combined with high impedances in the gate path can lead to parasitic turn-on of the MOSFET. With very short connections and a strong gate driver, almost perfect switching can be achieved.

The gate drive signals are created with analyzing the voltage levels across the power MOSFETs, to determine the exact timing when to turn on the switch. Once fully turned on, the voltage drop across the switch can be calculated as R_DSON * I_OUT, so the lower the R_DSON the lower the voltage drop, and hence the power dissipation (neglecting switching losses for a moment). It is crucial to determine the right moment to turn on and off the power switches, to avoid conduction of the body diode, which forces commutation of the current and of course has a higher voltage drop.

Below table compares the results obtained with the different rectifiers, based on 400W output power (24V at 17A), and a junction temperature of 100 degrees Celcius:

Click on image to enlarge.

It is interesting to note that the power dissipation in the output rectifiers correlates to the output current, not to the output voltage. The higher the output current, the more a synchronous rectification solution is advantageous. A practical limit for Schottky diodes is around 10A, beyond which the power dissipation in the rectifiers becomes quite large, as the forward voltage does depend somewhat on the current. For higher output voltages however, Schottky diodes may be better since currents are smaller and no driver circuits are required.

Power Supply System

The identical form factor for both primary and secondary side modules allow for a very elegant mechanical solution Click on image to enlarge.

Under EuP guidelines, a new methodology to measure power supply efficiency has been adopted, measuring the input and output power at 25%, 50%, 75%, and 100% of the rated output power. Using this method, the power supply shows an efficiency of 93.8%.

Conclusion

Modern industrial power supplies can significantly benefit from the new power supply modules available today. Power density and efficiency, as well as reliability and robustness are the main improvements, as shown by this design. And this significantly improves the life cycle cost too!

Further literature:

_{[1] R. W. Erickson and D. Maksimovic, "Fundamentals of Power Electronics", Second Edition, Springer, 2001, Chapter 19, ISBN 0-7923-7270-0}

_{[2] Fairchild Semiconductor Application Note AN4151, "Half-bridge LLC Resonant Converter Design using FSFR-series Fairchild Power Switch (FPS)", www.fairchildsemi.com}

_{[3] Various, "Grosser Vergleichstest Industrie-Schaltnetzteile, Teil 1-3", ELEKTRONIK 08 / 09 / 10 / 2007}