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Cadence Low-Power solution enables Fujitsu Microelectronics tapeout of 65nm WiMAX design
"The CPF-enabled Cadence Low-Power Solution allowed us to raise the bar on low-power design, with more power saving and reduced turnaround time," said Nobuhiko Aneha, deputy general manager of the mobile solution division of Fujitsu Microelectronics Ltd. "This is a proven solution for us, and we will continue to deploy it for other low-power designs."
The development, first unveiled by Fujitsu Microelectronics at the Cadence DA SHOW/CDNLive conference in Japan, demonstrates that the Cadence Low-Power Solution continues to gain momentum as an essential production-quality, robust low-power design solution backed by real design tapeouts.
A number of technologies in the Cadence Low-Power Solution were responsible for the result. The automated power shut-off flow in Encounter digital implementation helped Fujitsu Microelectronics achieve about 50 percent reduction in physical design turnaround time compared to previous methodologies. The CPF-based Incisive Simulation technology allowed Fujitsu Microelectronics to run logic simulation of the power shutoff feature without requiring custom programming language interfaces (PLIs). The Cadence Conformal Low-Power software verified the low-power design rules through structural and functional verification, while both Incisive and Conformal low-power verification technologies contributed to the improved quality of silicon for this design.
"Since inception, the CPF-enabled Cadence Low-Power Solution has gained recognition in the industry for being able to deliver on real production designs," said Dave Desharnais, group director of IC Digital products at Cadence. "Cadence is delighted to be part of Fujitsu Microelectronics' recent successful design tapeout, and will continue to support Fujitsu Microelectronics in its low-power design methodology."
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