Cadence Design Systems, Inc. has launched the Cadence Encounter Digital Implementation System, a configurable digital implementation platform delivering scalability with complete support for parallel processing across the design flow.

The system also features an ultra-efficient new core memory architecture delivering higher-performance, higher-capacity design closure for single CPU operations. With the new system, designers are reporting improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices.

Along with enhanced performance and capacity, Encounter Digital Implementation System offers new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow. In addition, multiple new and enhanced implementation and design closure technologies are being introduced, including automated floorplan synthesis, end-to-end multi-mode multi-corner optimization, variation-tolerant and low power clock tree and clock mesh synthesis, high-capacity placement and optimization, 32-nanometer routing and manufacturing-aware optimization, signoff-driven implementation, and flip chip design features.

Using Encounter Digital Implementation System designers are able to achieve numerous levels of predictability, productivity, scalability, and flexibility from its unified and automated implementation environment for high performance, high-capacity design closure; low power, mixed signal and advanced node design; and signoff analysis. The extensibility and integration of the Encounter Digital Implementation System helps designers to achieve rapid technology adoption, and a faster, higher-quality ramp to volume production.

Describing the benefits of the Cadence solution, John F. Brown III, VP IC Engineering at Tilera, explained: "Tilera's TILEPro64 processor includes 64 general purpose cores each operating at up to 866 MHz with total chip power consumption under 20 watts, thus putting challenging requirements on timing and power. Encounter Digital Implementation System brings together all the related tools under one interface with easy data-sharing and powerful debug capabilities. We can now converge early in the chip development process, achieving faster design closure and meeting aggressive time-to-market goals for our networking, wireless, and digital multimedia applications."

Kun-Cheng Wu, Director of Design Development, Faraday Technology, said: "As a leader in SoC design services, Faraday has always been committed to designing chips that are not only high performance, but high power-efficiency as well. Encounter Digital Implementation System's low power technology exceeds our expectations in delivering a low-power implementation flow. The CPF-enabled Cadence Low Power Solution provides a full front-to-back solution that helps us significantly reduce power consumption in our designs".

The Encounter Digital Implementation System's advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization, make it a capable solution for leading-edge 45- and 32-nanometer designs " those with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1 GHz, ultra-low power budgets, and large amounts of mixed-signal content. The system provides comprehensive manufacturing-aware and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure.

www.cadence.com