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Tower and Jazz Semiconductor targets power management with scalable RDS(on) design tool
The TS18PM design kit technology claims to set a new standard for design flexibility by providing a wide range of process modules under one design kit environment. The capability to maximize design IP re-use over many market spaces with optimized die size/cost enables customers to reach markets at design cycle times considered unattainable only a few years ago. The Tower/Jazz BCD platform addresses 80 percent of the growing $11 billion power management IC market and targets applications such as leading-edge LED drivers, motor controllers, battery management, and Class-D amplifiers.
The TS18PM process offers high voltage LDMOS FETs that take advantage of 0.18-micron rules to reduce on-resistance and size of power cells, enabling optimization and the smallest possible die area for every power transistor versus competitive solutions. The process also includes a Y-FLASH zero mask adder multi-time-programming non-volatile memory (MTP NVM) solution from 64bits for trimming applications to 64 Kilobits for code storage applications. The TS18PM design kit includes 20 V-60 V scalable RDS(on) NLDMOS/PLDMOS devices as well as advanced 0.18-micron CMOS and bipolar NPN devices needed in today's complex power management chips. The kit also includes industry leading RF and Thermal modeling, predictive parasitic extraction switch, high voltage ESD solutions, and dense 5 V and 1.8 V digital cell libraries for 'digital intensive' designs. In addition, the kit allows the ability to streamline the process to 20 layers (TS35PM) for Power stage dominated designs.
Dr. Avi Strum, Specialty Business Unit Vice President, Tower Semiconductor, said: "The design kit will serve as a springboard to our newest power platform offerings of more than 100 V and Ultra Low RDS(on) devices."
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