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In recent years, power consumption has moved to the forefront of ASIC and system-on-chip (SoC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Furthermore, with every new process generation, leakage power consumption increases at an exponential rate.
A wide variety of power-efficient design techniques have been developed to address the various aspects of the power problem, including the use of clock gating, multi-switching threshold (multi-Vt) transistors, multi-supply multi-voltage (MSV), substrate biasing, dynamic voltage and frequency scaling (DVFS), and power shut-off (PSO).
However, 'Low-power and Power-Efficient Design' isn't just something that can be 'bolted on' at the end of the development process. Power, timing, and area are overlapping and potentially conflicting goals that need to be balanced throughout the flow. To meet aggressive design constraints and schedules, it is no longer sufficient to consider power only in the implementation phase of the design. The size and complexity of today's ICs make it imperative to consider power throughout the complete design process, from the chip/system architectural phase; through the implementation architecture phase; through design (including micro-architecture decisions); and all the way to implementation with power-aware synthesis, placement, and routing. Similarly, to prevent functional issues from surfacing in the final silicon, power-aware verification must be performed throughout the development process including final signoff.
To address power issues, today's design environments boast a wide variety of sophisticated power-aware tools and methodologies. However, even with the high level of automation that such tools provide, applying these techniques can require substantial effort, introduce new risks, and can increase the complexity associated with design, implementation, and verification.
In order to ensure smooth adoption of power-efficient design techniques, we need a way to enable all team members regardless of power experience to utilize the capabilities at their disposal without needing to become power experts, or to learn by trial and error.
This article describes the concept of a 'low-power kit' that when applied as part of a complete power-efficient design solution enables teams with and without power expertise to adopt advanced design techniques efficiently and effectively. A low-power kit gathers expert knowledge and best practices to: eliminate common problems; establish flows to ensure tools and technologies are applied to achieve the best results; and establish processes to ensure predictability.
Capturing power intent
A key part to enabling a complete front-to-back power aware design methodology is a way to capture the power intent of the design which is independent from the functional description. In this article we will assume the usage of the Common Power Format (CPF), managed under the auspices of the Silicon Integration Initiative (Si2) consortium's Low-Power Coalition, to provide a mechanism to capture architects' and designers' intent for power management, enable the automation of advanced power efficient design techniques and allow 'what-if' exploration to take place without RTL changes.
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Figure 1: CPF provides a holistic specification of power intent used throughout design, implementation, and verification
The benefit of using CPF within a low-power kit is the ability to drive the design, verification, and implementation from a single 'golden' power intent description (Figure 1). A high level of automation within the tools around this central description eliminates many of the error prone tasks typically associated with low-power design.
A representative design
A variety of different considerations must be taken into account when creating a low-power kit. First and foremost, it is necessary to create a representative design that embraces all the low-power aspects of the typical designs you will be working on. This allows the different aspects of the kit to be proven out, demonstrated, and provides adopters with a well defined sandbox in which to experiment and learn. Additionally, this design can act as a pipe-cleaner whenever tool or silicon vendor changes are made.
As an example, consider an IEEE 802.11-based wireless access device comprising various interfaces and peripherals. At the core of this device will be an SoC containing a variety of functional blocks. A block diagram of the functions comprising such a representative design is shown in Figure 2. This will typically include some hard macros such as a microprocessor core, as well as a variety of first and third-party IP (both verilog and VHDL) - many of which may utilize power saving techniques.
Since power is not determined by digital logic alone, the representative design includes not only digital logic, but also a number of analog/mixed-signal (AMS) blocks, such as a phase-locked loop (PLL) in the clock generator and any physical-layer (PHY) interfaces.
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Figure 2: Functional block diagram for an example representative design
Modularization eases adoption
To facilitate understanding, enable an incremental adoption and mixed flows, the kit should be partitioned into a number of main categories; for example Design Environment, Low-Power Techniques, Design Creation, Physical Implementation, Verification (including signoff), and Management. In turn, each of these categories should comprise a number of discrete modules and flows (Figure 3). Design and verification teams then need to use only those modules appropriate for their particular design.
Where applicable, each module should include: background information pertaining to this aspect of the design, best practices, checklists, recommended flows, scripts to demonstrate the flows, analysis to understand the impact on the design, training material, and documentation.
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Figure 3: The low-power kit should feature a number of categories, modules and flows
Design environment
This category should cover everything required to establish a complete low-power design environment for a new project, including infrastructure, tools, IP components, and detailed checklists and dependencies.
Some example modules are:
* Library Developmentand Qualification
Ensures the necessary library information including low-power cells, views, and databases are available for successful design flows;
* Process Selection
Defines how low power affects process selection and what is needed based on design requirements;
* Infrastructure
Provides data management and system infrastructure to ensure a smooth power aware implementation.
Power-efficient design techniques
This category should cover the various power-efficient design techniques that may be employed in a design and that are supported by the design environment. Tradeoff analysis should also be performed to determine the most appropriate techniques to apply, and to quantify there impact on the design power profile.
Some example modules are:
* Multi-Threshold Voltages
When and how to use this highly automated technique effectively;
* Low-Power Clocking
As a major contributor to power consumption, managing clocks effectively is key to a power aware implementation;
* Multi-Supply Multi-Voltage
Defines the benefits and pitfalls of MSV and what is needed to implement it in a design;
* PowerShut-Off
PSO has substantial power benefits, but it needs to be applied appropriately as it affects all areas of the design process;
* Dynamic Voltage and Frequency Scaling
DVFS techniques may also have substantial power benefits, but ensuring that the performance-voltage-frequency feedback mechanism works correctly can be a challenge.
Management
This category should cover the various facets of managing a power-efficient design, from planning a verification strategy, defining metrics and estimation techniques, to implementing a low-power engineering change order (ECO) methodology.
Some example modules are:
* Low-Power ECO Methodology
Track all data and flow dependencies to ensure that late-stage changes do not cause problems including hierarchal ECOs and pre and post mask ECOs;
* Planning, Metrics and Analysis
Predictability is ensured through proper metrics and planning, and must be considered throughout the design process;
* Design Reuse
Guidelines and requirements to ensure that internal and external IP can be utilized.
Design Creation
This category should cover all design creation aspects of the flow, including performing architectural tradeoffs among power, timing, and area, along with best practices for success with designs employing MSV and/or PSO techniques.
The modules included in this category might be as follows:
* Architecture Tradeoff
Compare different techniques and how they affect total power within your class of designs;
* RTL Design
Covers what can be done in RTL to affect power consumption as well as how the different techniques are codified;
* CPF Creation
Effective power intent representation using the Common Power Format including templates for your design styles;
* Low-Power Synthesis
How synthesis affects the power process and how to implement the most effective synthesis for a low-power design;
* Power-Aware DFT
Power affects both normal modes of operation and test and must be considered throughout to ensure that power related functionality is tested, and that testing does not artificially exceed power limits.
The flows covering these modules should utilize the golden RTL and CPF files together with simultaneous optimization of all constraints (timing, area, and power) to create an optimized netlist that includes all of the relevant low-power structures including level-shifters, isolation cells, and retention logic.
Physical Implementation
This category should cover all the aspects of physical design from netlist through design signoff. As with Design Creation, the golden CPF file should be used to communicate power intent throughout the flow.
Some example modules are:
* Prototyping and Parasitic Correlation
Multiple iterations of floorplan optimization may be needed on the road to timing closure. Accurate power aware parasitic scaling between detailed extraction and prototyping extraction speeds closure;
* Power Planning
Proper selection of a power distribution scheme (grid or ring) must be taken into account for power-aware and non power-aware blocks;
* Low-Power Floorplanning
Determine the best location for sensitive blocks. Rules may govern that blocks with the same voltage are located in close proximity or closer to pad I/Os, for example;
* Timing and Signal Integrity Closure
Even if power intent is considered to be the most important, timing and SI specifications must be met to obtain a functional design.
Verification
The importance of verification within a low-power flow can best be illustrated by considering just a few of the challenges when utilizing the PSO technique. At the functional level we need to ensure that powered down logic does not cause invalid data to propagate, that any necessary state is retained during power down, and that power sequencing ensures successful power-up. During implementation we need to verify that the appropriate isolation cells and other power structures are in place. Finally, during power grid signoff, we need to make sure that any in-rush current during power-on of the PSO block does not corrupt surrounding logic.
Some example modules are:
* Low-Power Functional Verification
Power intent directly affects functionality, so the design must be verified in the context of the power implementation using techniques such as power-aware simulation and assertion-based verification (including formal functional verification);
* Low-Power Formal Implementation Verification
Defines a process to ensure that the low-power implementation chosen is correct and consistent through all design transformations;
* Power-Grid Signoff
Prior to signoff, verify that the static and dynamic behavior of the power grid meets all requirements for correct operation;
* Full-Chip Signoff
Ensure that the final physical signoff is power aware.
Summary
Utilizing a kit-based approach as part of a complete solution to power-efficient design as described here, together with a way to capture the designs power intent (such as CPF), is a highly effective way to capture and communicate power-efficient design knowledge throughout an organization, allowing designers of different experience levels to effectively and efficiently adopt advanced power-efficient design techniques.
About the author:
Neil Hand is Cadence Design Systems' Director, Solutions Marketing.
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