In early days, getting a lower power CPU typically meant sacrificing
functionality, running at reduced clock speeds, or waiting for new low
power process technologies to reduce both Standby and
Active power. This is no
longer the case by any means, and the processor landscape has changed
dramatically.
Advances in processing technology along with innovative chip designs
and high-granulation power management software have brought entirely
new families of low power processors where designers no longer need to
make sacrifices in their system designs.
Of course, no one device "has it all," so engineers must consider
their system requirements carefully and then examine the now expanding
range of low power processors to see which one best fits their
application requirements.
This article summarizes the state of the art with a
product-selection matrix (Table 1, below). One axis shows the following
design criteria that are of chief concern to system designers:
* Power
* Performance
* Integration
* Time to Market
* Price
The other axis lists the major processor variants based on their
feature sets. This article then explains the meaning behind the generic
criteria and how various types of processors earn their rankings in the
table.
This information achieves two goals: first, it alerts system
designers to the newest types of processors on the market, some of
which are relatively new and about which they might not be familiar;
second, given this ever larger product palette, it helps them narrow
down the selection of the best chip for a given design.
Examine the criteria
To help you sort through the various low power devices, refer to Table
1, which grades the major types of low power processors according to
several criteria of interest to designers. The first thing to note is
that these criteria are all closely interrelated.
For instance, integrating a large number of functions on a chip such
as multiple cores, analog features, large memories or many peripherals
can reduce overall system power, cost and time to market. Extensive
integration of this nature, though, can add unwanted power consumption
and make programming more complicated, thus extending time to market.
Criterion #1: Power
For many of today's designs, this is the single most important
criterion. In portable products, extended battery life is a big
consumer plus. In many infrastructure applications, lower power
translates to less heat dissipation " and heat-dissipation "envelopes"
can be the limiting factor for channel density or feature additions.
There are also designs with a power budget such as USB-operated
products or automotive aftermarket products running from a car battery
that are allocated only a certain milliwatt budget for operation.
Power should be more properly viewed from a systems perspective. The
right mix of peripherals on a chip results in more overall system power
savings not only because off-chip devices consume extra power, but also
because it takes a lot more power to move data across traces on a PC
board than it does to move data within a device itself.
For individual devices, energy efficiency starts with the inherent
benefits of process technology, but this is only the beginning of what
advanced processors offer in this regard. Power consumption can be
broken into two main modes: first, active power consumption, which is
performed with transistor switching and takes place during ongoing data
processing; second, static power consumption, which takes place when
either limited or no data processing takes place and various components
go into a type of Sleep mode.
Several techniques are used within active power management:
* Dynamic
voltage and frequency scaling (DVFS). Here, clock rates and
voltages are lowered by software command depending on the performance
required by the application scenario.
For instance, even though the ARM on a multimedia processor might be
able to run at 600 MHz, all that power is not required in every case.
Instead, software can select from predefined operating performance
points that run the processor at specific rates.
* Adaptive
voltage scaling (AVS). This is based on the fact that silicon
manufacturing yields parts with a distribution of performance
capabilities; for a given frequency requirement, some devices (known as
"hot" devices) can achieve that level of performance with a lower
voltage than can "cold" devices.
In this situation, a processor senses its own performance level and
adjusts voltage supplies accordingly to compensate for variations in
processing, temperature and silicon degradation.
* Dynamic power
switching (DPS). This determines when a section of a device has
completed its current tasks, is not needed at the moment, and puts it
into a low power state. An example of this granulated power control is
when a processor enters a low power state while waiting for a DMA
transfer to complete.
Static power management takes place when either limited or no data
processing occurs, selected components can drop into a very low power
mode, and where the system waits for a wakeup event.
Handled by a technique known as static leakage management, it can
result in several low power modes from Standby to full Power Off. The
choice of which low power static mode is chosen depending on what
degree of memory retention and/or a fast wakeup time is needed.
Thanks to these features, most low power processors spec a standby
power in the range of 15 mW and a peak operational power below 400 mW.
However, some fixed-point
digital signal processors drop those figures to 0.50 mW standby and
75 mW peak even though it contains a FFT coprocessor, as much as 320k
bytes of memory and I/O peripherals.
In the table, most of the devices implement many if not all of these
power-saving features and get an "excellent" rating. The ones listed as
"good" are the highest performing chips, generally with multiple cores,
which naturally draw somewhat more power.
